Senior/Staff Design Engineer- SOC Timing
Posting Date : 26 Nov 2021 | Close Date :24 Feb 2022

SoC Timing


·         Work with system engineers on timing requirements and feedback on optimization.  

·         Work on SoC timing constraint, synthesis and timing closure.

·         Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains 

·         Conduct formal verification for release comparison.

·         Support back-end implementation on timing violation analysis and fix. 

·         Support scan insertion and optimization.

·         Support on power structure and power optimization.   


·         Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

·         Familiar with ASIC design flow

·         Experience in logic synthesis, static timing analysis, timing closure

·         Good understanding of DFT and Power structure.

·         Familiar with UNIX/ Linux environment and scripting

·         Good communication and interpersonal skills

·         Strong analytical and problem-solving skills

Specialization : Electronics/Semiconductor
Type of Employment : Permanent
Minimum Experience : 5 Years
Work Location : Singapore

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