Senior Physical Design Engineer
Posting Date : 13 Nov 2018 | Close Date :11 Feb 2019
Hands on experience in physical design and cadence & ICC physical design flow.

Good understanding of ASIC Designs (Block & SOC level)

Good understanding of deep sub-micron and DFM issues and layout techniques.

Should have work experience and understanding in CMOS process technologies 14nm and below.

Static timing analysis concepts and understanding of different library constructs

Responsible for timely and quality execution of physical design.

Constantly drive layout efficiency and quality by identifying productivity improvements.

Scripting skills in Perl, Skill is a plus.

Excellent verbal and written communication skills, including ability to effectively communicate with internal and external customers

Must be able to work under pressure and meet deadlines, while maintaining a positive attitude

Ability to work independently and to carry out assignments to completion within parameters of instructions given, prescribed routines, and standard accepted practices

Specialization : Electronics/Semiconductor
Type of Employment : Permanent
Minimum Experience : 4 Years
Work Location : Singapore

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