Digital IC Design Verification Engineer
Posting Date : 14 Jun 2019 | Close Date :12 Sep 2019

Digital IC Design Verification Engineer


Job Requirements

  • Bachelor/Master Degree in Computer/Electrical or Elecrtronics Engineering with 3+ years of related experience.
  • Strong background in ASIC Design Flow [RTL to GDS] 
  • Strong coding skill in Verilog/VHDL for synthesisable RTL and behavioral modeling. SystemVerilog, Verilog-AMS is a plus
  • Strong verification skills using SVA, UVM, OVM, DFT.
  • Familiar with Linux Environment (shell scripting and linux gnu tools).
  • Familiarity with Cadence/Mentor Graphics/Synopsys environment is a plus.
  • Scripting language experience a plus (perl, Makefile, bash, tcl, ... etc.).
  • Familiar with C coding, MATLAB is a plus.        
  • Familiar with ECO flow, FMEA is a plus.
  • Able to work independently and in a team environment.
Specialization : Engineering
Type of Employment : Permanent
Minimum Experience : 3 Years
Work Location : Malaysia

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