POSITION DETAIL

 
Senior Staff Logic Engineer
Posting Date : 06 Feb 2020 | Close Date :06 May 2020


Senior Staff Logic Engineer

Job Description:

You will have the opportunity to directly involved in defining the latest generation of DDR PHY IP for SOC application latest process node.

 

In this position, your responsibilities will include but not be limited to:

·         Develop high performance and low power DDR I/O micro-architecture specification or pre-silicon verification for the next generation computing memory architecture.

·         Developing Register Transfer Level RTL coding and/or pre-silicon verification environment/test-bench.

·         Collaborate closely with micro architects, logic/analog designers and physical designers.

·         The successful candidate requires a strong technical background in micro-architecture design, logic/verification methodology.

·         Need to be passionate about working in a dynamic environment where the expectation is to contribute in any activity that makes the business successful.

·         Candidate must have strong communication skills verbal and written, teamwork skills, be a self-starter, and have the capability of managing a dynamic work environment.

Qualifications:

·         Candidate must have a Bachelor, Master or PhD Degree in Computer Engineering, Electrical Engineering, Computer Science or related field.

·         Candidate will have 10+ years of hands-on experience with Logic Design and/or Pre-Silicon Verification

·         Candidate must possess strong fundamentals on the following area:

o    Experience with designing High Speed I/O Design and Mixed signal design. Possess strong fundamental knowledge of HW description language (Verilog and assertion coding) and logic simulation. Experience in IP integration is an added advantage.

o    Have strong fundamental knowledge in JEDEC specification, DDR architecture [(LP)DDR 4/5], and have extensive coding experience that includes logic+behavioral modelling SV coding.

o    Experience with post silicon debug and IO training.

o    Knowledge of digital design methodologies and tool flow (CDC, Lint, UPF, Fishtail, or GLS). Able to interpret and analyze report and provide solution to violations. Exposure/ability on tools setup and configuration is added advantage.

o    Knowledge of custom logic design. Experiences in high frequency and low power design is an added advantage.

o    Have experience in power aware design, UPF & multi-power domain checks.

o    Knowledge of synthesis and static timing analysis.

 
Specialization : Electronics/Semiconductor
Type of Employment : Permanent
Minimum Experience : 8 Years
Work Location : Malaysia
  

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