DFT Lead
Posting Date : 01 Oct 2020 | Close Date :30 Dec 2020

DFT Lead


Job Description:


Key Responsibilities include but not limited to


o Scan RTL architecture, design and methodology

o Perform scan coverage analysis and debug with Spyglass-DFT or other ATPG tools

o Scan RTL and GLS test validation to ensure quality design

o generate test patterns using industry standard tools, analyze and drive the improvements to test coverage

o Leading DFT team of 3-4 people and ensuring successful DFT implementation and verification within project timelines & also ensuring quality checks

o Collaborate with various stakeholders in architecture, IP, structural design, SoC RTL, and post-Silicon teams



• Requirement : 

o  7+ years' experience in DFT/Test in design flow

o  Understanding of  ATPG process, scan insertion, MBIST,..

o  Knowledge in RTL integration and validation methodologies

o  Understanding of Scan/ATPG collaterals

o  Familiar with Scan design, methodology, coverage analysis and test validation

o  Tcl/Tk/Perl to automate design process and improve efficiency

o  Knowledge of Synthesis/Scan stitching, STA, ATPG and MV design an advantage

o  Knowledge of Synopsys DC/DFT Compiler, Primetime and UPF an advantage

o Familiar with UNIX, and well-versed in Verilog or C Programming

o independent problem solving, debugging various simulation failures, formal verification etc.

o Ability to communicate well with counterparts and key stakeholders including cross-site partners

Specialization : Electronics/Semiconductor
Type of Employment : Permanent
Minimum Experience : 7 Years
Work Location : India

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