(Senior) Physical Design Engineer
Posting Date : 09 Nov 2020 | Close Date :07 Feb 2021

Physical Design Engineer



To provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).

In order to ensure successful tapeout, active participation in working with frontend and integration team is required.


·         Bachelor’s/ Master’s in Electrical Engineering with hands-on experience in back-end physical design and verification

·         Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues

·         Experience in top-level back-end physical design, mainly top-level floorplanning and partitioning, congestion analysis, placement optimization, clock-tree synthesis and timing closure

·         Proficient in static timing analysis (PrimeTime)

·         Proficient in programming/scripting with good coding experience in Tcl/Perl/Python.

·         Possesses good working ethic, good verbal and written communication skills

·         Familiar with tools such as Synopsys IC Compiler/Cadence Encounter and Primetime

·         Good knowledge on EM/IR-Drop/crosstalk analysis (PTSI, Redhawk), formal or physical verification (Calibre) will be an advantage

·         Singaporeans are welcome to apply

Specialization : Electronics/Semiconductor
Type of Employment : Permanent
Minimum Experience : 3 Years
Work Location : Singapore

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