Posting Date : 02 Jan 2019 | Close Date :02 Apr 2019

Job Description

CW will assist the DE Leads in executing DFT (Design for Test) tasks including scan insertion, ATPG, coverage analaysis and scan simulations 

Verification of Mixed Signal IP tests such as PCIe, PLL etc..

Preferred Skills:

DFT experience in SOC Design, DFT concepts & ATPG

Proficiency in VHDL/Verilog RTL skills, test bench creation & verification and EDA tools for DFT verification

Proficiency in Perl/C/C++

Knowledge in test development and Product Engineering

Specialization : Electronics/Semiconductor
Type of Employment : Contract
Minimum Experience : 3 Years
Work Location : Singapore

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